The present invention relates to a semiconductor memory provided with a flash write function.
An image DRAM is provided with a block write function that enables rewriting of information stored in a plurality of memory cells, which are connected to the same word line, at once. However, unlike a VRAM (video RAM), the image DRAM is not provided with a block write function, which rewrites the cell information of every memory cell connected to the same word line at once. In recent years, there is a demand for image DRAMs, which are used in digital cameras, digital video cameras, and the like, to be provided with the flash write function so that the image DRAM can adapt to multiple functions.
FIG. 7 is a schematic diagram illustrating a cell array structure of a conventional image DRAM. During a block write operation of the image DRAM, the cell information of memory cells 100 selected by column selection lines CL0, CL1, which are connected to selected word lines WL0, WL1 and column decoders 101, is rewritten at once.
During the block write operation, the loads applied to the column decoders 101 increase in comparison to a normal write operation and delays the leading edges of the signals in each of the selected column selection lines CL0, CL1. This is because the column decoders 101 must select a large number of the column selections lines CL0, CL1 and drive many column gate transistors 102. Thus, the block write time is longer than the normal write time.
FIG. 6 is a schematic diagram illustrating a cell array structure of a VRAM. During a flash write operation of the VRAM, plural pieces of cell information are rewritten by simultaneously driving flash write transistors 103, which are connected to bit lines BLZ, BLX, with flash write word decoders 104.
However, in addition to word lines WL and a main word decoder 105, the VRAM requires flash write transistors 103, flash write word decoders 104, and word lines FWL, which connect the flash write transistors 103 and the flash write decoders 104. This increases the circuit area of the VRAM. Thus, when the VRAM flash write function is incorporated in the image DRAM, flash write transistors and flash write word decoders increase the circuit area of the image DRAM.
Clock-synchronous type semiconductor memories (called SDRAM) are normally used in recent DRAMs. Since a clock-synchronous type semiconductor memory performs acquisition of external addresses and external commands, input and output of data, and internal circuit operations in synchronism with a system clock, operations at extremely high speeds are enabled. The SDRAM is further provided with a burst operation function. The information of a plurality of memory cells connected to a word line of a designated row address is held by a plurality of sense amplifiers. The sense amplifiers are sequentially selected by column addresses. This reads and writes data at a high speed. However, when memory cells connected to different word lines of the same cell array block are continuously selected, a relatively long time is necessary to read and write data.
In response to the demand for semiconductor memories having a higher speed, a DRAM that performs row access operation in a pipelined manner (hereafter referred to as FCRAM (fast cycle RAM)) has also been proposed. Such type of semiconductor memory reads and writes data at a high speed even if the row addresses are changed during the reading and writing of data. The FCRAM is a synchronous DRAM that has an extremely short operational cycle (e.g., 20 nanoseconds) and synchronously acquires external commands and external addresses in synchronism with a system clock signal. Further, the FCRAM inputs and outputs data in synchronism with the leading edges and trailing edges of the system clock to further increase speed. The synchronous DRAM (especially, FCRAM) is an optimal image DRAM since it operates at high speeds. Accordingly, it would be effective if the FCRAM is provided with the flash write function. However, the incorporation of the above VRAM flash write circuit would enlarge the circuit area. Further, the load applied to the column decoders would increase during flash write operations. Thus, it would be difficult to ensure the writing of flash data just by employing the VRAM flash write circuit.
It is an object of the present invention to provide a semiconductor memory that enables flash writing without increasing the circuit area.
To achieve the above object, the present invention provides a method for writing data to a semiconductor memory device. The semiconductor memory device includes a plurality of bit lines connected to a common data line by a plurality of column gates, a plurality of column selection lines for controlling the opening and closing of the column gates, a plurality of words lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The method includes the steps of selecting one of the plurality of word lines, and simultaneously activating the plurality of column gates with the plurality of column selection lines. Data of the common data line is written to the plurality of memory cells connected to the selected word line via the plurality of column gates at once. During the step of simultaneously activating the plurality of column gates, the plurality of column selection lines are simultaneously selected at a timing that is earlier than a timing for selecting one of the plurality of column selection lines during a normal write operation.
The present invention also provides a semiconductor memory device including a plurality of column selection lines for controlling the opening and closing of a plurality of column gates, a plurality of bit lines connected to a common data line by the plurality of column gates, a plurality of words lines, a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines, a column decoder connected to the plurality of column selection lines to simultaneously select the plurality of column selection lines during a flash write mode, and a timing pulse generation circuit for providing the column decoder with a timing pulse signal during the flash write mode at a timing that differs from a normal write mode.
The present invention further provides a semiconductor memory device including a plurality of words lines, a word decoder connected to the plurality of word lines, a plurality of bit lines extending perpendicular to the plurality of word lines, a plurality of sense amplifiers respectively connected to the plurality of bit lines, a plurality of column selection lines extending perpendicular to the plurality of bit lines and parallel to the plurality of word lines, a column decoder connected to the plurality of column selection lines, and a plurality of column gates for connecting a common data line to the plurality of bit lines with the associated column selection lines. The plurality of column gates are arranged along the plurality of column selection lines.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.